1. Field of the Invention
The present invention relates to an oscillation circuit device including a phase locked loop circuit (hereinafter referred to as a PLL circuit) which applies feedback control to an input reference signal to control the phase thereof.
2. Description of the Related Art
There has heretofore been known an oscillation circuit device which, when a reference signal from the outside is not inputted, generates and outputs an oscillation signal thereinside and when the reference signal is inputted from the outside, detects the reference signal, controls the phase thereof by a PLL circuit and outputs an oscillation signal.
A circuit diagram of a related art oscillation circuit device 400 is illustrated in FIG. 4.
The related art oscillation circuit device 400 is equipped with a power supply terminal 101, a ground terminal 102, constant current circuits 171 and 172, a PMOS transistor 122, switches 150, 151, and 154, an inverter circuit 153, a current control oscillator 113, a frequency division circuit 114, a phase frequency comparator 111, a charge pump circuit 112, a pulse detection circuit 110, and a filter circuit 174. The constant current circuit 171 is equipped with a PMOS transistor 120 and a first current source 140. The constant current circuit 172 is equipped with a PMOS transistor 121 and an NMOS transistor 131. The filter circuit 174 is equipped with a capacitance 161.
The above-described oscillation circuit device 400 has the function of performing oscillation signal switching in the following operations.
In a first mode in which a reference signal REF is not inputted to a REF terminal 103 from the outside, the pulse detection circuit 110 outputs LOW, and the switches 150 and 154 are ON, and the switch 151 is OFF. Since the PMOS transistors 120 and 122 configure a current mirror circuit through the switch 150, a drain current I1 and a current I3 of the respective PMOS transistors become currents proportional to each other. Further, the current I1 is equal to a current IB1 of the first current source 140. Consequently, the current control oscillator 113 outputs an output signal CLK of a frequency proportional to the current IB1 from a CLK terminal. Since the switch 151 is OFF in a state in which the reference signal REF inputted to the REF terminal 103 from the outside is not given, and the oscillation is made autonomously from the outside (which will be defined as a self-running state), the constant current circuit 172 does not affect the currents I1 and I3. Further, since the PMOS transistors 120 and 121 configure a current mirror circuit through the switch 150, a drain current I1 and a current I2 of the respective PMOS transistors become currents proportional to each other. At this time, since the switch 154 is ON, a gate and a drain of the NMOS transistor 131 are connected to each other, and electric charges based on the current I2 are charged in the capacitance 161. Thereafter, a gate voltage determined by the current I2 and the characteristics of the NMOS transistor 131 is generated at the gate of the NMOS transistor 131, and the current I2 flows into the NMOS transistor 131 with the completion of charging to the capacitance.
When the reference signal REF is inputted to the REF terminal 103 to enter a second mode, the pulse detection circuit 110 detects the reference signal REF and outputs HIGH to turn OFF the switches 150 and 154 and turn ON the switch 151. At this time, a PLL circuit for adjusting the phase of the reference signal REF by the phase frequency comparator 111, the charge pump circuit 112, the filter circuit 174, the constant current circuit 172, the current control oscillator 113, and the frequency division circuit 114 starts to operate. The NMOS transistor 131 which functions as a V/I conversion element V/I-converts an output voltage VCP of the charge pump circuit 112 to generate a drain current and supplies the drain current to the PMOS transistor 121. Since the PMOS transistors 121 and 122 configure a current mirror circuit, a drain current I2 and a current I3 of the respective PMOS transistors become currents proportional to each other. The current I2 in a steady state is controlled by the generally-known negative feedback operation of PLL circuit in such a manner that the frequency of the reference signal REF and the frequency of a feedback signal FB_CLK as the output of the frequency division circuit 114 become equal to each other. The current control oscillator 113 outputs an output signal CLK of a frequency proportional to the current I2 from the CLK terminal.
A technology of adding a constant current circuit to a PLL circuit and charging a capacitance of a filter circuit has been illustrated in Patent Document 1.
[Patent Document 1] U.S. Pat. No. 8,174,332 Specification